The Ethernet 1000BASE-X PCS/PMA or SGMII has updated reset logic in v11.5 and later of the core.
1) In transceiver.v/vhd, RXBUFRESET input has been grounded to avoid possible conficts in the RXBUFRESET being issued while GTRXRESET is still being completed.
2) The MMCM reset input was changed to hold the MMCM in reset until the CPLL has locked.
3) (Xilinx Answer 52135) 500 ns delay needed for GTTXRESET and GTRXRESET.
4) Additionally, in v12.0, v11.5 and v11.4, mmcm_locked was not connected to GT tx_startup_fsm and rx_startup_fsm. This has been corrected in v13.0 and later of the core. For a work-around see, (Xilinx Answer 55360).