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AR# 57210

14.6 EDK, AXI Ethernet v3.01a - Incorrect 'clk_rx' Constraints


When implementing AXI Ethernet core, the following warning is issued:

WARNING:ConstraintSystem:190 - The TNM 'clk_rx', does not directly or indirectly drive any flip-flops, latches and/or RAMS and cannot be actively used by the referencing Period constraint 'TS_gmii_rx_clk'.
If clock manager blocks are directly or indirectly driven, a new TNM and PERIOD are derived only if the PERIOD constraint is the only referencing constraint and if an output of the clock manager block drives flip-flops, latches or RAMs. 

The constraint that is causing the issue is in the <project>_ethernet_wrapper.ncf file generated by the tool:

NET "*/rx_mac_aclk_int" TNM_NET = "clk_rx";


This warning is due to the KEEP attribute being removed from HDL. 

The KEEP attribute is required in an EDK+ISE flow but is not required in an EDK+Vivado flow.

Since there is a single database which the design is picked from, a fix can be part of only one flow.

For an EDK+ISE flow, the work-around is attached. 

To apply the work-around:

1) Download the tri_mode_eth_mac_block_gmii.vhd attached to this Answer Record.

2) Go to <Xilinx Install Directory>\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_ethernet_soft_temac_wrap_v3_01_a\hdl\vhdl and replace the tri_mode_eth_mac_block_gmii.vhd with the one you just downloaded.

Note: Always make a backup of the original file.

Revision History:
8/22/2013 - Initial Release


Associated Attachments

AR# 57210
Date 11/24/2014
Status Active
Type General Article
  • AXI Ethernet
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