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AR# 57227

14.6 EDK - Changing the SPI clocks appears to corrupt the clocking


If I attempt to generate a netlist for a PS-based system, the following error occurs:

ERROR:EDK:3900 - issued from TCL procedure "zynqconfig_do" line 34 processing_system7_0 (processing_system7) - MHS file editing for Zynq related parameters is not allowed. Please use Zynq tab in XPS for PS configuration.
ERROR:EDK:440 - platgen failed with errors! make: *** [implementation/spi_test_processing_system7_0_wrapper.ngc] Error 2

How can I resolve this issue?


This is a known issue and will be fixed in a future release of the tools.

To work around the problem, copy the files that are attached at the end of this answer record into the following location: \ISE_DS\ISE\data\zynqconfig\spi\.

After copying the files, close and restart XPS.


Associated Attachments

Name File Size File Type
spi0_preset.xml 11 KB XML
spi1_preset.xml 13 KB XML
AR# 57227
Date 09/27/2013
Status Active
Type Known Issues
  • Zynq-7000
  • ISE Design Suite - 14
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