MIG 7 Series DDR3 RDIMM designs set the RC1 Clock Driver Enable control word to enable or disable the four output clocks in the for the SSTE32882 register chip located on the RDIMM. For single rank and dual rank designs, MIG only enables two clocks to conserve power. However, for the Micron MT9JSF25672PZ, the default clock drivers enabled are set incorrectly and may cause initialization failures in hardware.
The SPD module on the RDIMM can be read to determine which specific clock outputs are used and should be enabled, but MIG does not have the capability to read from the SPD so to resolve this issue all 4 clock drivers are enabled.
To work around the issue, the following RTL changes can be made inside mig_7series_v2_0_ddr_phy_init.v: