If you are using the ModelSim Simulation Flow in the VC709 Connectivity Targeted Reference Design (v2013.2), you may experience some errors that prevent the ModelSim simulator from running all the way through simulation.
An example of what can occur in the ModelSim console is below:
# Top level modules ten_gig_eth_pcs_pma_ip # Model Technology ModelSim SE-64 vlog 10.2c Compiler 2013.07 Jul 18 2013 # ** Error: /export/ssd/proj/Cheetah_FPGA/devel/mliang/Cheetah/z_VC709_XC7VX690T-2FFG1761CES_fpga_PCIe_ptypes/v7_xt_conn_trd/ip_cores/dma/netlist/eval/dma_back_end_axi_enc.v(1): near "XlxVHYEB": syntax error, unexpected IDENTIFIER, expecting class # ** Error: /export/ssd/Mentor/Modelsim_se_10_2_c/modeltech/linux_x86_64/vlog failed. # Error in macro /export/ssd/proj/Cheetah_FPGA/devel/mliang/Cheetah/z_VC709_XC7VX690T-2FFG1761CES_fpga_PCIe_ptypes/v7_xt_conn_trd/vivado/project_1/xt_connectivity_trd.sim/sim_1/behav/board.do line 394 # /export/ssd/Mentor/Modelsim_se_10_2_c/modeltech/linux_x86_64/vlog failed. # while executing # "vlog +define+USE_PIPE_SIM=1 +define+SIMULATION=1 +define+USE_DDR3_FIFO=1 +define+USE_XPHY=1 +define+NW_PATH_ENABLE=1 +define+x4Gb=1 +define+sg107E=1 ..."
In 2013.2, running the QuestaSim / ModelSim simulation will require a different NWL DMA model than the one included in the Vivado project by default.
To run a QuestaSim / ModelSim simulation:
NOTE: This solution is also described in the readme.txt of the VC709 Connectivity TRD design zip file.
Answer Number | Answer Title | Version Found | Version Resolved |
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51901 | Virtex-7 FPGA VC709 Connectivity Kit - Known Issues and Release Notes Master Answer Record | N/A | N/A |
AR# 57325 | |
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Date | 10/28/2013 |
Status | Active |
Type | General Article |
Devices | |
Boards & Kits |