Version Found: MIG 7 Series v1.9
Version Resolved: See (Xilinx Answer 54025)
MIG 7 Series DDR3 VHDL designs fail during write calibration when the pin-out has a bank containing Addr/Cont groups in T0, T1, and T2 byte lanes and a data group in byte lane T3. This affects VHDL designs ONLY. Identical MIG 7 series designs with the language set to Verilog will pass calibration successfully.
When write calibration fails due to this issue, it fails with a late write pattern similar to XXXXFF00AA5555AA. The expected Write Calibration pattern is FF00AA5555AA9966.
This is an rtl issue with the assignment of the CTL_BYTE_LANE parameter calculation within the user_design/rtl/phy/mig_7series_v*_*_phy_top.vhd module. The issue is the CTL_BYTE_LANE parameter calculation in the function CTL_BYTE_LANE_W does not consider byte group T2 when the number of Address/Control byte lanes is 3. The evaluation of this calculation is different between the VHDL and Verilog RTL. This issue is resolved in the attached patch. Included in the patch are instructions on applying the patch to generated MIG 7 Series designs.
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