Version Found: v2.5
Version Resolved and other Known Issues: See (Xilinx Answer 45723)
When Virtex-6 FPGa Integrated Block for PCI Express core is configured for Endpoint application, the bus/device/function number for the device will change upon Configuration Type 0 and Type 1 accesses.
By definition, Endpoint devices should not act upon Type 1 accesses as it is intended for Downstream ports only (i.e., PCIe switches). Xilinx PCIe core will respond to Type 1 Configuration accesses with an "Unsupported Request" (Completion with UR status). However, the bus/device/function number at the User Interface is accidentally updated.
Currently, there is no work-around to this issue. However, it is rare that an Endpoint receive Type 1 Configuration accesses in a system because these packets should be terminated at the switches (i.e., switches or Root Complex will not send these packets to Endpoints as part of enumeration).
To ensure that the system is behaving normally in embedded systems (custom Root Complex or Switches), the designer should ensure that Type 1 Configuration access is not made to an Endpoint, or ensure that Endpoint receives a Type 0 Configuration access last.
09/05/2013 - Initial release