We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 57404

Vivado - How can I find the compile order of my HDL files for Simulation or Synthesis?


I would like to verify that my HDL files are being compiler in the expected order.  Is there a way to do this in Vivado tools?


You can use the following commands to get synthesis or simulation compile orders for a full project or an IP core.

full projects:

get_files -compile_order sources -used_in synthesis
get_files -compile_order sources -used_in simulation

specific IPs:

get_files -compile_order sources -used_in synthesis  -of [get_files <ip>.xci]
get_files -compile_order sources -used_in simulation -of [get_files <ip>.xci]

The usage of the -compile_order switch allows Vivado to take into account more complex logic of exactly what files will be used for a synthesis or simulation flow (e.g. if regular source set are used from within a simulation set or not, complex file ordering rules that can change based on header files or other language options etc.)

AR# 57404
Date 09/09/2013
Status Active
Type General Article
  • Vivado Design Suite