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A design that uses a divider with input and/or output widths greater than 64-bit causes an assertion failure during SystemC co-simulation.
The following message is issued:
Assertion failed: DIN0_WIDTH <= 64, file C:/Xilinx/Vivado_HLS/2013.2/common/technology/generic/SystemC/AESL_comp.h, line 877
The same design will pass Verilog and VHDL RTL co-simulations, export of IP-XACT succeeds, and RTL and post-implementation simulations can be successfully run in the Vivado tool using the VHLS generated project files.
As a result, RTL co-simulations can be used as a work-around.
Please bear in mind that the SystemC co-simulation uses simulation models, and the implementation tools use the RTL (Verilog or VHDL).
This issue will be fixed in Vivado HLS 2013.3.
Answer Number | Answer Title | Version Found | Version Resolved |
---|---|---|---|
47429 | Xilinx Vivado HLS Solution Center - Top Issues | N/A | N/A |
AR# 57454 | |
---|---|
Date | 10/20/2014 |
Status | Active |
Type | Known Issues |
Tools |