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AR# 57472

2013.2 Vivado Placer - [Place 30-129] message does not provide sufficient detail regarding root cause of placement failure

Description

My design is failing with the following placement error for a BUFMRCE driving a BUFR. 

I have these buffers constrained to the same clock region which should be routable according to the error message. 

Why does this error occur?

ERROR: [Place 30-129] Unroutable Placement! A BUFMRCE / BUFR component pair is not placed in a routable site pair. The BUFMRCE component can use the dedicated path between the BUFMRCE and the BUFR if the BUFMRCE is placed in the same clock region, the clock region above or the clock region below as the BUFR. In parts with multiple Super Logic Regions(SLR), the BUFMRCE and the BUFR components are required to be in the same SLR.
   U_rtmac_fpga/U_rtmac_20g_data_path_dp1/U_serdes_pktbus_2lane_if_dual/U_serdes_pktbus_2lane_if0/genblk1.U_serdes_pktbus_2lane_gt/U_DATA_IF_BUFMR (BUFMR.O) is locked to BUFMRCE_X1Y4 (in SLR 0)

The loads are distributed to 1 user pblock constraints. 

In addition, there are 0 loads not in user pblock constraints.

Solution

There are additional restrictions for BUFMRCE to BUFR connections in the same clock region that are not currently mentioned in the message text. 

If the BUFMRCE and BUFR are in the same clock region, one free PHASER_IN_PHY site must be available for a route-thru in that clock region or the net must also have a load that is a PHASER_IN.PHASERREFCLK pin.

In this case, all Phaser sites in the clock region were occupied and that is the reason the placer error occurred.

A change request has been filed to add this information to the message text.
AR# 57472
Date Created 09/16/2013
Last Updated 11/06/2014
Status Active
Type General Article
Devices
  • Artix-7
  • Kintex-7
  • Virtex-7
Tools
  • Vivado Design Suite - 2013.2