AR# 57570

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LogiCORE IP Discrete Fourier Transform (DFT) v4.0 (Rev. 2) - When behavioral simulation is run on the DFT v4.0 IP core with Cadence IES in 2013.3, some outputs do not agree with the C model output

Description

When behavioral simulation is run on the DFT v4.0 (Rev. 2) IP core with Cadence IES in the Vivado 2013.3 tool, some outputs do not agree with the C model output. In mismatching cases, the LSB of the IP core output will mismatch by 1 LSB. This is due to a difference in rounding behavior in the Cadence IES simulator libraries.

Solution

This is a known issue with Discrete Fourier Transform v4.0.

One work-around is to simulate with a post-synthesis or post-implementation netlist. For further details, see the Vivado documentation.

Alternatively, another simulator such as Vivado Simulator can be used to perform behavioral simulation of the IP.

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AR# 57570
Date 10/21/2013
Status Active
Type General Article
Tools
IP
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