I have configured my AXI FIFO block to use "Common Clock Distributed RAM" for the implementation type but when the design is implemented it appears to use a block RAM instance.
Why does this occur?
This is a known issue where the XCO file being created by System Generator for the IP core is incorrect and does not contain the correct parameter setting, and as a result it defaults to "Common Clock Block RAM".
This will lead to unexpected resource utilization. This issue does not occur when using Vivado System Generator and only occurs with ISE System Generator.