The tool inserts the BUFIO2(In MAP stage) into the netlist between IBUFDS and DCM, but this inserted bufio2 cannot be seen in schematic as well device view of implemented design.
I am able to see this BUFIO2 in the fpga_editor and netgen output (simulation netlist).
Is this the expected behavior?
This display issue is due to the limitation of logical to the physical database and is the expected behavior.
The schematic of the PlanAhead tool is based on the logical database, which does not contain the bufio2 added by MAP.