This answer record is a guide to debugging the Comma Alignment, TX/RX buffer or buffer bypass problems.
Note: This answer record is part of the Xilinx HSSIO Solution Center (Xilinx Answer 37181).
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Comma Detection and Alignment
Serial data must be aligned to symbol boundaries before it can be used as parallel data. Without proper alignment, the incoming 8B10B data will not decode correctly.
If alignment is lost at any time, there will be a burst of disparity (RXDISPERR) and not in table (RXNOTINTABLE) errors.
Make sure that the final "target" alignment is one that corresponds to Table 4-33 in the user guide (shown below).
RXSLIDE can be used to override the automatic comma alignment and to shift the parallel data.
RXSLIDE is driven High for one RXUSRCLK2 cycle to shift the parallel data by one bit. Be aware that RXSLIDE must be Low for at least 32 RXUSRCLK2 cycles before it can be used again.
Useful Answer Records
|(Xilinx Answer 46200)||RXBYTEISALIGNED is not always reliable|
|(Xilinx Answer 47054)||User defined comma for SONET not allowed|
|(Xilinx Answer 43242)||GTX RXSLIDE does not work in simulation with 13.1|
|(Xilinx Answer 50530)||Can RXBYTEREALIGN be used as RXSLIDE completion status signal?|
Very few problems are reported with Clock Correction for the 7 series. The user guide explains it well and the example designs do a good job of setting it up.
Useful Debug Ports
The TX/RXBUFSTATUS should be monitored to make sure that the buffers do not overflow. If and when they do, data will be lost.
The following are the potential causes:
Buffer bypass is an advanced use mode and should only be used if low latency is required. The 7 series has had some problems with the TX phase initialization.
Useful Debug Ports
Xilinx Answer Records
|(Xilinx Answer 43883)||How does RXCDRLOCK work?|
Non Integer Data Recovery Unit (XAPP875) - The NI-DRU extends the lower data rate limit to 0 Mb/s and the upper limit to 1,250 Mb/s, making embedded high-speed transceivers the ideal solution for true multi-rate serial interfaces.