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AR# 57743

Xilinx HSSIO Solution Center - Design Assistant Debugging Equalization and Margin Problems

Description

This answer record discusses debugging of the Equalization and Margin.

Note: This answer record is part of the Xilinx HSSIO Solution Center (Xilinx Answer 37181).

The HSSIO Solution Center is available to address all questions related to HSSIO.

Whether you are starting a new design or troubleshooting a problem, use the HSSIO Solution Center to guide you to the right information.

Solution

Equalization and Margin Analysis

For 7 Series and UltraScale devices, the equalization varies widely depending on the application and board layout. It is important to make a selection of the equalization settings based on channel design and especially the channel loss at the Nyquist frequency.

Problems commonly result from leaving the default settings chosen by the wizard instead of tailoring the settings to the intended design. In theory, no channel will be error free, so to choose equalization settings, a target Bit Error Rate (BER) should be chosen.

See (Xilinx Answer 57449) - Bit Error Rate 101.


The IBIS-AMI model used with some of the available Signal Integrity tools (such as SiSoft's QCD) will model the internal equalization and give an estimate of the BER that a given channel can achieve.

It can also be used to optimize the equalization setting for 7 series devices.

See the Serial Link Signal Analysis White Paper (WP428):

http://www.xilinx.com/support/documentation/white_papers/wp428-7Series-Serial-Link-Signal-Analysis.pdf


The two main hardware tools for margin analysis are IBERT and Eye Scan.

Eye Scan analysis can be designed into a system to measure the data eye on the fly which can save a lot of debug time.

XAPP743 "Eye scan with MicroBlaze MCS" describes eye scan; see also Serial Link Signal Analysis.

You will also find the In-system Eye Scan of a PCI-Express Link XAPP1198 useful and (Xilinx Answer 60024) explains how to expand this to systems other than PCI Express.


Do not leave the TX side out of the optimization process.

Optimizing the emphasis (pre and post) on the sending side is often all that is needed to get the desired results and occasionally it is the only adjustment that can fix a weak TX channel.

AR# 57743
Date Created 09/30/2013
Last Updated 09/30/2015
Status Active
Type Solution Center
Devices
  • Artix-7
  • Kintex-7
  • Virtex-7
  • More
  • Kintex UltraScale
  • Virtex UltraScale
  • Less