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AR# 57760

MIG 7 Series QDRII+ - Stage 1 calibration will always pass even if no edges are detected

Description

Version Found: v1.6
Version Resolved: See (Xilinx Answer 54025)

MIG 7 Series QDRII+ stage 1 calibration of read clock with respect to Q will always pass even if no edges are detected and the taps have maxed out. Only during Stage 2 calibration will failures be detected and cause calibration to stop.

Solution

When debugging calibration failures, it is important to validate that stage 1 passed as expected using the enabled debug signals referenced in the 7 Series FPGAs Memory Interface Solutions v2.0 User Guide (UG586):
http://www.xilinx.com/support/documentation/ip_documentation/mig_7series/v2_0/ug586_7Series_MIS.pdf

Revision History
10/01/2013 - Initial release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
54025 MIG 7 Series - IP Release Notes and Known Issues for Vivado 2013.1 and newer tool versions N/A N/A
AR# 57760
Date Created 10/01/2013
Last Updated 10/01/2013
Status Active
Type Known Issues
Devices
  • Kintex-7
  • Virtex-7
IP
  • MIG 7 Series