(Xilinx Answer 56332) mentions COMMON_CFG needs to be updated.
Is this required for the Virtex-7 FPGA Gen3 Integrated Block for PCI Express core?
The first two of the three update attributes that are mentioned in (Xilinx Answer 56332) are the same as in the current core release (v2.1/v1.6). The third attribute COMMON_CFG can be updated but this is not required for Virtex-7 FPGA Gen3 Integrated Block for PCI Express core. Users can choose to update the settings or not without impacting the performance and compliance of the core.
10/03/2013 - Initial release