We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Page Bookmarked

AR# 57796

2013.4 Vivado IP Flows - [Synth 8-1769] error when reloading elaborated design


I have an IP core in my design. I have opened the elaborated design.
If I re-generate/generate the output products of the IP core, the status indicator of the open elaborated design shows that it is out of date.
However, when I reload the elaborated design using the "Reload" button, the below error occurs:

[Synth 8-1769] cannot open verilog file /proj_dir/my_project/my_project.srcs/sources_1/ip/mult_gen_0/mult_gen_0_stub.v<
[Common 17-104] Zip archive /proj_dir/my_project/my_project.runs/mult_gen_0_synth_1/mult_gen_0.dcp not found.

Why does this happen?


This error occurs when the OOC run related to the IP core is not yet completed. 

The error indicates that the DCP (more specifically, the stub) for the elaborated design is not yet available.

The error is not seen if you reload the elaborated design after the OOC run completes.

In Vivado 2014.1, a wait_on_run for the IP cores OOC run is issued when the Reload Elaborated Design button is clicked.

This allows the OOC run to complete and then have the elaborated design open.
AR# 57796
Date 12/09/2014
Status Archive
Type Known Issues
  • FPGA Device Families
  • Vivado Design Suite - 2013.3