AR# 57854

2014.1 Vivado Synthesis - Some patterns of asymmetric BRAM inference are not successful.


Starting from 2014.1 Asymmetric BRAM inference has been supported.

However, it has been found that some patterns of asymmetric BRAM inference are not successful.

Failure can occur in one of the following ways.

1. An Error is displayed by Vivado Synthesis.

ERROR: [Synth 8-2913] Unsupported Dual Port Block-RAM template for ram_reg.


ERROR: [Synth 8-2914] Unsupported RAM template for RAM ram_reg.

2. RAM is implemented in registers.

The following warning is displayed in Synthesis.

Warning: Trying to implement RAM "ram_reg" in registers. Block RAM or DRAM implementation is not possible for one or more of the following reasons : 1: RAM has multiple writes via different ports in same process. If RAM inferencing intended, write to one port per process. 2: Unable to determine number of words or word size in RAM. RAM "ram_reg" dissolved into registers

3. RAM is not implemented as expected.

For example, if more BRAMs are inferred than expected.


Not all patterns of Asymmetric BRAM coding are currently supported.

The asymmetric RAMs have to match the coding style guides in UG901.

he asymmetric BRAM coding examples are added in UG901 v2014.1.

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
52264 Does Vivado Synthesis support Asymmetric read/write port width block RAM inference? N/A N/A
AR# 57854
Date 06/06/2014
Status Active
Type General Article
Tools More Less