AR# 57866

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Artix-7 FPGA AC701 Evaluation Kit - Constraints for Ethernet on AC701

Description

What I/O standard is required for Ethernet connections on the Artix-7 FPGA AC701 Evaluation Kit?

Solution

The implement Ethernet connections on the AC701, HSTL_I_18 IO standard must be applied.

The required pins, which should have HSTL_I_18 associated with them, are:

  • PHY_TX_CTRL
  • PHY_TXD[3:0]
  • PHY_TX_CLK
  • PHY_RX_CTRL
  • PHY_RXD[3:0]
  • PHY_RX_CLK


As the HSTL standard requires a VREF, the internal Vref constraint must be applied:

INTERNAL_VREF_BANK13=0.90

For ease of use, the full XDC syntax for these constraints is given below:

set_property PACKAGE_PIN U22      [get_ports PHY_TX_CLK]

set_property IOSTANDARD HSTL_I_18 [get_ports PHY_TX_CLK]

set_property PACKAGE_PIN T15      [get_ports PHY_TX_CTRL]

set_property IOSTANDARD HSTL_I_18 [get_ports PHY_TX_CTRL]

set_property PACKAGE_PIN T17      [get_ports PHY_TXD3]

set_property IOSTANDARD HSTL_I_18 [get_ports PHY_TXD3]

set_property PACKAGE_PIN T18      [get_ports PHY_TXD2]

set_property IOSTANDARD HSTL_I_18 [get_ports PHY_TXD2]

set_property PACKAGE_PIN U15      [get_ports PHY_TXD1]

set_property IOSTANDARD HSTL_I_18 [get_ports PHY_TXD1]

set_property PACKAGE_PIN U16      [get_ports PHY_TXD0]

set_property IOSTANDARD HSTL_I_18 [get_ports PHY_TXD0]

set_property PACKAGE_PIN U21      [get_ports PHY_RX_CLK]

set_property IOSTANDARD HSTL_I_18 [get_ports PHY_RX_CLK]

set_property PACKAGE_PIN U14      [get_ports PHY_RX_CTRL]

set_property IOSTANDARD HSTL_I_18 [get_ports PHY_RX_CTRL]

set_property PACKAGE_PIN V14      [get_ports PHY_RXD3]

set_property IOSTANDARD HSTL_I_18 [get_ports PHY_RXD3]

set_property PACKAGE_PIN V16      [get_ports PHY_RXD2]

set_property IOSTANDARD HSTL_I_18 [get_ports PHY_RXD2]

set_property PACKAGE_PIN V17      [get_ports PHY_RXD1]

set_property IOSTANDARD HSTL_I_18 [get_ports PHY_RXD1]

set_property PACKAGE_PIN U17      [get_ports PHY_RXD0]

set_property IOSTANDARD HSTL_I_18 [get_ports PHY_RXD0]

set_property INTERNAL_VREF 0.9    [get_iobanks 13]

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
51900 Artix-7 FPGA AC701 Evaluation Kit - Known Issues and Release Notes Master Answer Record N/A N/A
AR# 57866
Date 10/10/2013
Status Active
Type General Article
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