AR# 57873

PlanAhead - LVDS pin assignment issue on Bank 7 (Site P77 and P78) for Spartan-3 FPGA


The design is targeted to device sp3400-tw144-4.

I create the design in the PlanAhead tool and assign a LVDS differential port to site P77 and P78.

The following error occurs during implementation:

[Constraints 5] Cannot loc terminal 'lvds_p[1]' at site P77, Site PAD124 is not part of a diff pair ["C:\my_proj\project_3\project_3.runs\impl_1_2\.constrs\lvds_error.ucf":5]
[Constraints 5] Cannot loc terminal 'lvds_n[1]' at site P78, Site PAD123 is not part of a diff pair ["C:\my_proj\project_3\project_3.runs\impl_1_2\.constrs\lvds_error.ucf":7]

Why does this error occur?


The sites P77 and P78 are differential ports. However, the PlanAhead tool does not show them as a differential pair and is unable to comply with the constraints.

To work around this issue, implement the design in Project Navigator or use the ISE command line tools.

AR# 57873
Date 11/04/2013
Status Active
Type Known Issues