General Description: FPGA Express 3.2 now has a Verilog Pre-processor that allows the use of the following directives:
'ifdef 'else 'endif `define macros with and without arguments
This pre-processor is not enabled automatically, so users will have to set a switch to turn it on. It is not turned on by default because when it is on, it will ignore the //synopsys translate_off compiler directive.
To enable this feature, select Synthesis -> Options and set the proper option.
In standalone FPGA Express, check the box next to: "Enable Verilog Pre-processor"
In the Foundation Project Manager, select "Enable" under the option: "Verilog 'ifdef support"
In Foundation ISE, right-click on 'Synthesize' and select properties. Click on the box next to 'Enable Verilog Preprocessor'.
In the fe_shell, open your project and set the environment variable: