AR# 57945


UltraScale FPGA Gen3 Integrated Block for PCI Express - Release Notes and Known Issues


This answer record contains the Release Notes and Known Issues for the UltraScale FPGA Gen3 Integrated Block for the PCI Express Core and includes the following:

  • General Information
  • Known and Resolved Issues
  • Revision History

This article is part of the PCI Express Solution Centre

(Xilinx Answer 34536)Xilinx Solution Center for PCI Express

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Please seek technical support via the PCI Express Board. The Xilinx Forums are a great resource for technical support. 

The entire Xilinx Community is available to help here, and you can ask questions and collaborate with Xilinx experts to get the solutions you need.


General Information

Supported devices can be found in the following three locations:

  • Open the Vivado tool -> IP Catalog, right-click on the IP and select Compatible Families.
  • For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado design tools.
  • UltraScale FPGA Gen3 Integrated Block for PCI Express Product Guide (PG156)
Version Table

This table correlates the core version to the first Vivado design tools release version in which it was included.

Core VersionVivado Tools Version
v4.4 (Rev7)2020.1
v4.4 (Rev6)2019.2
v4.4 (Rev5)2019.1
v4.4 (Rev4)2018.3
v4.4 (Rev3)2018.2
v4.4 (Rev2)2018.1
v4.3 (Rev1)2017.2
v4.2 (Rev3)2016.4
v4.2 (Rev2)2016.3
v4.2 (Rev1)2016.2
v3.1 (Rev1)2014.4
v3.0 (Rev1)2014.2


Design Advisory

(Xilinx Answer 64404)Design Advisory for UltraScale FPGA Gen3 Integrated Block for PCI Express (Vivado 2015.1, 2014.4.1) - Link Training failure due to PHYSTATUS not responding to PHY Operations after Device Configuration


Tactical Patch

The following table provides a list of tactical patches for the UltraScale FPGA Gen3 Integrated Block for PCI Express core applicable on corresponding Vivado tool versions.

Download fromCore Version (after installing the patch)Vivado VersionIssues Fixed
(Xilinx Answer 64404)v4.0 (Rev1)2015.1(Xilinx Answer 64404), Update #1 in (Xilinx Answer 64838)
(Xilinx Answer 64875)
v4.0 (Rev2)
2015.2(Xilinx Answer 64875)
(Xilinx Answer 65744)v4.1 (Rev. 65744)2015.3(Xilinx Answer 65744)
(Xilinx Answer 65831)v4.1 (Rev. 65831)2015.3(Xilinx Answer 65744), (Xilinx Answer 65831)
(Xilinx Answer 66347)v4.1 (Rev. 66347)2015.4(Xilinx Answer 66347)
(Xilinx Answer 67111)v4.2 (Rev. 67111)2016.1(Xilinx Answer 67111)
(Xilinx Answer 67422)v4.2(Rev. 67422)2016.2(Xilinx Answer 67422)
(Xilinx Answer 69308)v4.3 (Rev 69308)2017.1(Xilinx Answer 69308)
(Xilinx Answer 69477)v4.3 (Rev 69477)2017.1 / 2017.2(Xilinx Answer 69477)
(Xilinx Answer 70061)v4.4 (Rev 70061)2017.3(Xilinx Answer 70061)
(Xilinx Answer 76024)v4.4 (Rev 76024)2020.2(Xilinx Answer 76024)

Known and Resolved Issues

The following table provides known issues for the UltraScale FPGA Gen3 Integrated Block for PCI Express core, starting with v1.0, initially released in Vivado 2013.3.

Note: The "Version Found" column lists the version the problem was first discovered.

The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Answer RecordTitleVersion FoundVersion Resolved
(Xilinx Answer 76024)Gen3 Designs with "Auto RxEq" option enabled might train down to Gen1Vivado 2020.2Not Resolve Yet; Tactical Patch Provided
(Xilinx Answer 70061)PIPE Simulation fails when PIPELINE STAGE of 2 is enabledv4.4v4.4(Rev1)
(Xilinx Answer 69477)Timed (unsafe) between source clock sys_clk and destination clock pipe_clkv4.3 / v4.3 (Rev1)v4.4
(Xilinx Answer 69308)GT DRP Arbiter Blockv4.32017.2
(Xilinx Answer 68081)ERROR: [DRC 23-20] Rule violation (HDTC-6) Non-stage-one logic illegally placed - Non-stage-one logicv4.2(Rev1)v4.3
(Xilinx Answer 67422)Link up failure in Gen3 rate after multiple resetsv4.2(Rev1)v4.2(Rev2)
(Xilinx Answer 67111)Issue with MSI-X Table Offset Valuesv4.2v4.2(Rev1)
(Xilinx Answer 66347)ASPM Support Updatev4.1 (Rev1)v4.2
(Xilinx Answer 65946)Critical warnings CDC-1 and CDC-7 on the input port clock to user_clkv4.1v4.2
(Xilinx Answer 65831)GT DRP Ports disabled when Falling Edge Receiver Detect is selectedv4.1v4.1(Rev1)
(Xilinx Answer 65744)Enabling both MSI and MSI-X in the same designv4.1v4.2
(Xilinx Answer 65776)ERROR: [DRC 23-20] Rule violation (REQP-1881) Tandem_design_fails_with_flash_programmingv4.1v4.1(Rev1)
(Xilinx Answer 65587)CRITICAL WARNING: [Timing 38-282] Negative SETUP slack violationv4.1v4.1(Rev1)
(Xilinx Answer 64875)PCIe link up failure due to deassertion of CPLLLOCK during resetv4.0 (Rev1)v4.1
(Xilinx Answer 64718)Incorrect refclk_buf location for XCVU095 - FFVC2104, XCVU190 - FLGA2577 and XCVU125 - FLVC2104v4.0v4.0(Rev1)
(Xilinx Answer 62668)Example design simulation and synthesis might fail for the VHDL version of the corev3.1v3.1 (Rev1)
(Xilinx Answer 62471)Timing violations when implementing 2014.2 upgraded design in 2014.3v3.1NA
(Xilinx Answer 60072)Timing Violations with non X0Y0 PCIe locationsv3.0v3.0(Rev1)
(Xilinx Answer 60299)The host system fails to detect PF1v3.0v3.0 (Rev1)
(Xilinx Answer 59946)PERSTn signal usage for Virtex UltraScale devicesv3.0v3.0(Rev1)
(Xilinx Answer 59900)Post Synthesis/Implementation Netlist Functional/Timing Simulation Supportv3.0v4.0
(Xilinx Answer 73402)UltraScale PCIe - Gen2 using CPLL does not link up when in-system IBERT is enabledv4.4 (Rev6)v4.4 (Rev7)


Other Information

(Xilinx Answer 59901)Enabling GT Wizard mode in Vivado
(Xilinx Answer 61492)I/O Standard selection for PERSTn pins
(Xilinx Answer 64761)Bitstream Loading across the PCI Express Link in UltraScale Devices for Tandem PCIe and Partial Reconfiguration
(Xilinx Answer 65940)[DRC 23-20] Rule violation (HDTC-12) CONFIG cells must be in stage one
(Xilinx Answer 68134)UltraScale and UltraScale+ FPGA Gen3 Integrated Block for PCI Express - Integrated Debugging Features and Usage Guide
(Xilinx Answer 69453)Hot Plug Support
(Xilinx Answer 66497)Simulation in ModelSim / QuestaSim responds to all Cfg requests with UR
(Xilinx Answer 69195)MWr TLP request response with stage-1 bitstream
(Xilinx Answer 71427)ERROR: [DRC REQP-1910] PCIE31_invalid_MCAPPERSTxB_driver
(Xilinx Answer 71355)Vivado ILA Usage Guide for UltraScale FPGA Gen3 Integrated Block for PCI Express
(Xilinx Answer 72053)How to set MCAP_FPGA_BITSTREAM_VERSION for Tandem
(Xilinx Answer 72175)Debug Questions for Link Training Issues


Revision History

10/23/2013Initial Release
12/18/2013Updated for 2013.4
04/16/2014Updated for 2014.1
07/15/2014Added (Xilinx Answer 61492)
10/08/2014Updated for 2014.3
11/24/2014Updated for 2014.4
04/15/2015Updated for 2015.1
06/24/2015Updated for 2015.2
07/04/2015Added Design Advisory Answer Record and Tactical Patch section
07/23/2015Added (Xilinx Answer 64875)
10/06/2015Updated for 2015.3
11/11/2015Added (Xilinx Answer 65940)
24/11/2015Updated for 2015.4
15/1/2016Added (Xilinx Answer 66347)
04/13/2016Updated for 2016.1
06/06/2016Added (Xilinx Answer 67111)
08/06/2016Updated for 2016.2
07/21/2016Added (Xilinx Answer 67422)
10/05/2016Updated for 2016.3
10/15/2016Added (Xilinx Answer 68081)
01/24/2017Updated for 2016.4
04/05/2017Updated for 2017.1
07/05/2017Updated for 2017.2
07/18/2017Added (Xilinx Answer 69477)
10/31/2017Added (Xilinx Answer 70061)
04/18/2018Added (Xilinx Answer 66497)
03/06/2019Added (Xilinx Answer 72053)
04/22/2020Added (Xilinx Answer 73402)
01/22/2021Added (Xilinx Answer 76024)

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AR# 57945
Date 02/23/2021
Status Active
Type Release Notes
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