The HDL Netlist code created from System Generator does not show the correct connections through the design when the "Bus Creator" block is used in a design and subsystem entities are reused in the HDL generated by Sysgen for that design.
Are there any work-arounds available to avoid this issue with ISE Sysgen?
This is a known issue affecting ISE System Generator. The issue does not occur in Vivado System Generator.
Work-arounds exist for ISE System Generator as follows:
% p = xlGetPrefs -> (this shows a list of already set Sysgen Prefs)
% xlSetPrefs(p) % n = xlGetPrefs -> (check to make sure new Sysgen Pref is set correctly)