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AR# 57964

Vivado Synthesis - Issue with VHDL Time data Type


The following code performs a division with two time data types in VHDL:

entity SimpleCounter is 
generic (
kStableClkPeriodNs  : time    := 25 ns
port (
end entity SimpleCounter;
architecture rtl of SimpleCounter is
constant kQpllLockTimeNs     : time := 1000000 ns;
constant kQpllLockFiltCount : integer := kQpllLockTimeNs / kStableClkPeriodNs;

However, the following warning occurs during Synthesis:

WARNING: [Synth 8-3512] assigned value '-30' out of range [../SimpleCounter.vhd:29]

Opening the resulting Synthesized Design shows that the design is completely trimmed out.


Lowering the number in the division allows Synthesis to correctly generate logic for the design. The following tests were run:

1. kStableClkPeriodNs (25 ns) & kQpllLockTimeNs (set to 1000 ns) No warning is generated.
2. kStableClkPeriodNs (25 ns) & kQpllLockTimeNs (set to 10000 ns) No warning is generated.
3. kStableClkPeriodNs (25 ns) & kQpllLockTimeNs (set to 100000 ns) No warning is generated.
4. kStableClkPeriodNs (25 ns) & kQpllLockTimeNs (set to 1000000 ns) Warning is generated and the Synthesized Design shows all logic trimmed.

Vivado Synthesis has a limitation to the precision that is supported for time that goes in accordance with the LRM, and this is the reason for the generation of the warning message and the design getting trimmed out.

Using time for integer calculations should be avoided and is not a recommended coding style supported by Vivado Synthesis.

The current work-around is to substitute the division for the resulting integer value (40000), which synthesizes correctly.

constant kQpllLockFiltCount : integer := 40000;
AR# 57964
Date 04/16/2014
Status Active
Type Known Issues
  • Vivado Design Suite