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AR# 57975

Vivado Synthesis - Issue with array of instances when using SystemVerilog unpacked arrays


There is an issue when passing unpacked array to array of instances.

Vivado Synthesis reports an error for the following piece of code:

output [7:0] q;
wire [7:0] tmp1 [3:0];
wire [7:0] tmp2 [3:0];
test inst[3:0]
        (   tmp1,
assign q = tmp2[0] | tmp2[1] | tmp2[2] | tmp2[3];

In the above sample code, unpacked array tmp2 is mapped to the output port "b" from a sub module test which is 8-bits wide.

The following error message occurs when the tool tries to connect the unpacked array tmp2 via the array of instances:

ERROR: [Synth 8-659] type mismatch in output port connection: bit [7:0]A[3:0] vs. bit [31:0]B [/../xxxx.v:15]
ERROR: [Synth 8-285] failed synthesizing module 'top' [/../xxxx.v:1]


To work around the issue, there are a couple of options:

  • Change the unpacked array tmp2 to packed array tmp2, and then pass it on to the array of instance. The above code will change as follows:
  • output [7:0] q;
    wire [7:0] tmp1 [3:0];
    wire [31:0] tmp2;

    test inst[3:0]
            (   tmp1,
    assign q = tmp2[7:0] | tmp2[15:8] | tmp2[23:16] | tmp2[31:24];  
  • Keep the unpacked array and do not use the array of instance, but instead, instantiate a sub-module representing the array bit slice.

    For example: In the above case, instantiate the sub module test 4 times representing each array bit slice (0, 1, 2, 3) and pass the apt array bit slice to tmp1 and tmp2 (0, 1, 2, 3).

This issue has been fixed in the 2017.3 release.

AR# 57975
Date 01/05/2018
Status Active
Type Known Issues
  • Vivado Design Suite
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