Setting loose timing constraints causes Vivado Synthesis to choose LUTRAMs instead of block RAM.
For example, setting false paths to ignore timing between READ and WRITE clocks causes synthesis to choose LUTRAMs over block RAM.
How can I work around this issue?
As it is an early stage of the entire flow, the Synthesis view of timing and constraints is not accurate enough to make all of the expected timing driven inference.
You can use Synthesis attributes to change the Synthesis behavior.
To work around the problem, specify the ram_style='block" in the HDL code for the memory that needs to be inferred into a block RAM.