General Description: FPGA Express 3.3 (a.k.a. Foundation Express 2.1i with Service Pack 2) has the ability to infer Shift Register LUTs for Virtex devices. Use the following code snippets in your HDL source to achieve these inferences.
These shift registers can be of any size. If less than 16 bits, Express will connect the address lines to VCC or GND to create a smaller shift register. If greater than 16 bits, Express will infer multiple SRL16 components to build the large shift register.
Any size shift may be inferred in Static Length Mode, but to use Dynamic Length Mode, the component must be instantiated.
Solution
1
The following VHDL code will infer an SRL16 component:
process (CLK) begin if CLK'event and CLK='1' then REG <= DIN & REG(15 downto 1); end if; DOUT <= REG(0); end process;
Add a clock enable signal to infer an SRL16E component:
process (CLK) begin if CLK'event and CLK='1' then if CE='1' then REG <= DIN & REG(15 downto 1); end if; end if; DOUT <= REG(0); end process;
2
The following Verilog code will infer an SRL16 component:
always @(posedge clk) begin int = {din, int[15:1]}; end assign dout = int[0];
Add a clock enable signal to infer an SRL16E component:
always @(posedge clk) begin if (ce) int = {din, int[15:1]}; end assign dout = int[0];