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AR# 58022

Vivado Synthesis - Netlist names for signals coming from VHDL record types have changed


Generated netlist names coming from VHDL signals of type record have changed between 2013.2 and 2013.3. They used to be called something like signal_reg_a[1] and now are referred to as signal_reg[a][1] where "a" is one of the fields of the record.

Is there a reason for this change?


This was a planned change in the tool as it was running into naming convention errors when the old method was used. This new naming style avoids those errors and is in line with other Synthesis and Simulation tools.
AR# 58022
Date 10/22/2013
Status Active
Type Known Issues
  • Vivado Design Suite
  • Vivado Design Suite - 2013.3
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