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AR# 58023

Vivado - Is there a "Generate Instantiation Template" option for HDL source files (Entities/Modules) in the Vivado tool?


In the ISE design tools, it was possible to open the Design Utilities and View the HDL Instantiation Template. 

It created a .vhi file (for VHDL) or a .vei (for Verilog) containing a component and instantiation template for the selected source.

Is there a similar feature in Vivado Design Suite?


Vivado Design Suite provides a "View Instantiation Template" feature for composite file (e.g., .xci, .bd and .xps design) source types. 

However, it does not have a menu option to create instantiation templates for user-created HDL sources.

In Vivado 2014.1, an app was added in the Vivado Tcl Appstore that helps to accomplish this task.

Install the Designutils app in the Tcl Appstore (Tools -> Xilinx Tcl Store) if it has not been previously installed.

The module should be set as top-level.
When it is elaborated or synthesized:

  • Run "xilinx::designutils::write_template" to create a stub, template or testbench.  
  • Run "xilinx::designutils::write_template -usage" for usage information.
AR# 58023
Date 10/06/2014
Status Active
Type General Article
  • Vivado Design Suite
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