When I run Vivado Synthesis on my design, I receive the following message:
The read address is actually registered, so it is synchronous read but it has a sync reset on it.
What is the root cause of the issue? Is the feature supported?
The synchronous reset on the read address register is the root cause of the block RAM inference failure.
Vivado Synthesis does not currently support this feature.
The INFO message is misleading here as the read address is actually synchronous but Vivado Synthesis fails to extract it due to the reset.
To work around the issue, the following options are available:
1. Use the following switch:
set_param synth.elaboration.rodinMoreOptions "rt::set_parameter doBramAddrRegResetTransform true"
This will pull reset from the address register so that it can be used to infer BRAM.
In addition if there is a max_fanout attribute on that register, remove it from the read address register.
2. Use the RAM templates provided in the Vivado Synthesis User Guide.