How do you optimally set the pblock size?
The pblock constraints provided in the example design XDC file place portions of the system-level design example into a bounded region of the selected device. The pblock forces packing of the soft error mitigation logic into an area physically adjacent to the ICAP site in the device. Most importantly, this maintains reproducibility in timing results.
Additionally, the pblocks improve resource usage; the pblock forces tighter packing and generates a resource usage summary that is helpful in estimating the FIT of the system-level design example. Furthermore, this tighter packing may reduce the FIT of the controller.
Once the controller is integrated in the system-level design, Xilinx recommends that the pblock constraints be resized to pack the logic tightly.