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AR# 58050

Vivado - ERROR: [HDL 9-806] Syntax error near "char". ["file":286]

Description

Vivado displays the following error when adding a .sv file to a project:

ERROR: [HDL 9-806] Syntax error near "char". ["file":286]

Solution

This error is issued because the .sv file contains a variable with a SystemVerilog keyword "char".

Changing this to use a non-keyword resolves the error.

AR# 58050
Date Created 10/21/2013
Last Updated 12/08/2014
Status Active
Type General Article
Devices
  • SoC
  • FPGA Device Families
Tools
  • Vivado Design Suite - 2013.3
  • Vivado Design Suite - 2013.2
  • Vivado Design Suite - 2013.1
  • Vivado Design Suite - 2012.4