AR# 58074

Design Advisory for 2013.3 Vivado IP Integrator - Block design containing a MIG IP fails validation after upgrade to 2013.3

Description

My block design (design_1.bd) contains a MIG IP in the design, but it fails to validate and errors similar to the following appear after I upgrade:

[BD 41-703] </mig_7series_1/memmap/memaddr> is mapped into </axi_datamover_1/Data_MM2S/SEG1>, but there is no path between them. Unmap the segment in the Address Editor GUI or use delete_bd_objs to remove it manually
[BD 41-703] </mig_7series_1/memmap/memaddr> is mapped into </axi_datamover_1/Data_S2MM/SEG2>, but there is no path between them. Unmap the segment in the Address Editor GUI or use delete_bd_objs to remove it manually
[BD 41-238] Port/Pin property CLK_DOMAIN does not match between /ui_clk2_90(dn_1_mig_7series_1_0_ui_clk) and /mmcm_ui_clk2_90/clk_out1(dn_1_mmcm_ui_clk2_90_0_clk_out1)

How can this issue be addressed?

Solution

If re-customization of the MIG IP block is needed, the following TCL commands must be entered into the TCL console after re-customization is complete:

set_property -name {CONFIG.XML_INPUT_FILE} -value  {} -objects [get_bd_cells mig_7series_0];
set_property -name {CONFIG.XML_INPUT_FILE} -value {mig_a.prj} -objects [get_bd_cells mig_7series_0]

Revision History
11/14/2013 - Initial release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
58339 Design Advisory Master Answer Record for Vivado IP Integrator N/A N/A
AR# 58074
Date 11/22/2013
Status Archive
Type Design Advisory
Tools
IP