AR# 58082

Description

The TRD delivered with the Virtex-7 FPGA VC709 Connectivity Kit is a x8 Gen3 endpoint design which has scatter gather DMA from Northwest Logic, dual DDR3 controllers each operating at 1866 Mbps, and four ten gigabit Ethernet MAC with 10GBASE-R physical layer.

The design operates in:

• Performance Mode (GEN/CHK)
• Performance Mode (Raw Ethernet)
• Application Mode

Also provided are Linux (32-bit and 64-bit Fedora 16) device drivers with user space application for traffic generation and consumption.

Release notes for this TRD can be found in the Solution section below.

Solution

Virtex-7 XT Connectivity Targeted Reference Design (v1.3) for 2014.3 with Production Silicon

Hardware

• VC709 Connectivity Kit (rev 1.0 with Production Silicon and other components in Kit)
• PC with PCI Express slot (x8 PCIe v3.0 compliant)
• Keyboard and Mouse

Software

• QuestaSim / ModelSim v10.2a
• Vivado 2014.3

Xilinx IP Versions Used 

Other Information / Troubleshooting:

• The graphical user interface does not show power number plots: This can happen when FPGA is reprogrammed leaving the earlier design accessing PMBUS controllers in an unknown state. 
• Unzipping the TRD zip file in Windows and copying over the unzipped folder to Linux leaves some files without execution permission. User has to manually do 'chmod +x <file name>' on a terminal to make the files executable.
• On Fedora 16 64-bit version, performance is observed to be lower when compared with Fedora latest versions( Fedora 17 and Fedora 18).
  
• Linux GUI is tested with JDK 1.7 version.
  
• The Linux GUI in TRD uses jfreechart as a library and no modifications have been done to the downloaded source/JAR.
  jfreechart is downloaded from http://www.jfree.org/jfreechart/download.html and is licensed under the terms of LGPL.
  A copy of the source along with license is included in this distribution.
  
• The TRD works on Virtex-7 XT production silicon
  
• The interrupt mode of operation of the Linux driver has been tested with Fedora kernel version 3.5
  
• The user can download the Fedora 16 64-bit OS from the link: http://www.fedoraproject.org.
  It is advised to install the full version of Fedora (DVD ISO image) on the machine with the PCIe slot in it.
  Refer to (UG962) for more details on the PCIe host machine.
  
• The TRD synthesis and implementation steps can take a long time, depending on the machine used. This is best saved for an overnight task.
  
• This TRD might have difficulty meeting timing if any changes are made to the RTL. This design should meet timing if used as-shipped with 2014.3.
  
• The 10G Ethernet MAC IP core requires a license to build the design.
  The license can be obtained by clicking on Evaluate or Order on the following page http://www.xilinx.com/products/intellectual-property/DO-DI-10GEMAC.htm 
  
• The 10G Ethernet PCS-PMA 10GBASE-R IP core requires a license to build the design.
  The license can be obtained by clicking on Evaluate or Order on the following page http://www.xilinx.com/products/intellectual-property/10GBASE-R.htm
  

Virtex-7 XT Connectivity Targeted Reference Design (v1.1) for 2013.2 with Production Silicon

Hardware

• VC709 Connectivity Kit (rev 1.0 with Production Silicon and other components in Kit)
• PC with PCI Express slot (x8 PCIe v3.0 compliant)
• Keyboard and Mouse

Software

• QuestaSim / ModelSim v10.2a
• Vivado 2013.2

Xilinx IP Versions Used 

Other Information / Troubleshooting:

• The graphical user interface does not show power number plots: This can happen when FPGA is reprogrammed leaving the earlier design accessing PMBUS controllers in an unknown state.
  Resolution: Power off the host machine and power cycle the VC709 board and this should be fixed.
• Unzipping the TRD zip file in Windows and copying over the unzipped folder to Linux leaves some files without execution permissions.
  You will need to manually use 'chmod +x <file name>' on a terminal to make the files executable.
• On Fedora 16 64-bit version, performance is observed to be lower when compared with the latest versions (Fedora 17 and Fedora 18).
• GUI is developed with JDK 1.6 version. A few APIs are depreciated in JDK 1.7. You will need to modify the APIs or use JDK 1.6 to compile the GUI shipped along with the package.
• The GUI in TRD uses jfreechart as a library and no modifications have been done to the download source / JAR.
  jfreechart is downloaded from http://www.jfree.org/jfreechart/download.html and is licensed under the terms of LGPL.
  A copy of the source along with license is included in TRD distribution.
• The TRD works on Virtex-7 XT production silicon
• The interrupt mode of operation of driver has been tested with kernel version 3.5
• The user can download the Fedora 16 64-bit OS from the link: http://www.fedoraproject.org.
  It is advised to install the full version of Fedora (DVD ISO image) on the machine with the PCIe slot in it.
  Refer to (UG962) for more details on the PCIe host machine.
  
• The "promgen" and "impact" commands are not supported in Vivado 2013.2.
  The user needs to install ISE Lab Tools to generate the MCS file and for loading the image to PROM.
  Additionally, in order to program the BPI flash on the VC709, version 14.2 or 14.6 of the Lab Tools is necessary.
  Refer to (Xilinx Answer 55402) for additional details.
• In 2013.2, running the QuestaSim / ModelSim simulation will require a different NWL DMA model than the one included in the Vivado project by default.
  For details, see (Xilinx Answer 57325).
• Running the Vivado Simulator flow take a very long time to run and requires at least 8 GB of memory.
  This is best saved for an overnight task using batch or GUI modes.
• The TRD synthesis and implementation steps can also take a long time, depending on the machine used, and what configuration of the TRD you are building (FULL will take the longest).
  This is because it is using the Performance_Explore Implementation strategy, which is necessary for this version of the TRD to meet timing.
  The user can choose to use the Default Implementation for faster run-times, and use the design in hardware if the WNS (Worst negative slack) is < 300 ps.
• This TRD may have difficulty meeting timing if any changes are made to the RTL.
  It should meet timing as shipped by Xilinx when used in 2013.2.
• During Connectivity TRD setup, the device might not be recognized correctly if the TRD is not loaded into the BPI flash.
  For details, see (Xilinx Answer 57470).
• When Programming the board with VC709program.bat, the board might not be found.
  For details, see (Xilinx Answer 57431).

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