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AR# 58086

7 Series GTZ Transceiver Wizard in Vivado 2013.3 - Known Issues and Work-arounds

Description

This answer record covers known issues related to v3.0 of the 7 series FPGAs Transceivers Wizard targeting GTZ Transceivers in Vivado 2013.3 Design Suite.

Solution

1)  Missing XDC constraints when a south octal design has different userclk selections (CR: 740683).
This applies to the Virtex-7 HT XC7VH870T device.

Work-around: Since the clocking to the south octal and south beachfront module is different, the signals coming from octal to beachfront has to be ignored for timing. Please add false path constraint on those signals.

2)  Tool is unable to place BUFGs. The design is failing in place_design stage when there are large number of MMCMs and BUFGs in the design (CR: 741959).
This applies to the Virtex-7 HT XC7VH580T and XC7VH870T devices.

Work-around: Add location constraints to MMCM and BUFG in the design. For the BUFG locations, please see the excel at the bottom of this answer record.

3)  MMCM is not configured properly for scenarios when an OUTCLK from one lane is driving another lanes userclk with different linerate (CR:741088).
This applies to the Virtex-7 HT XC7VH580T and XC7VH870T devices.

Work-around: Set the proper DIVIDER and MULT values for the MMCM based on CLKIN period and CLKOUT period required. For calculations, see: http://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf.

Attachments

Associated Attachments

Name File Size File Type
GTZ_BUFG.xlsx 17 KB XLSX
AR# 58086
Date Created 10/22/2013
Last Updated 10/29/2013
Status Active
Type Known Issues
Devices
  • Virtex-7 HT
Tools
  • Vivado Design Suite - 2013.3
IP
  • 7 Series FPGAs Transceivers Wizard