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7 Series FPGAs Transceiver Wizard v2.6 - Release Notes and Known Issues
This answer record contains the Release Notes and Known Issues for the 7 Series FPGAs Transceiver Wizard v2.6, released with the ISE 14.6 and Vivado 2013.2 design tools.
- Version 2.6
- New Protocol Templates added for GTH - Interlaken
- Updated Port and Attribute Settings to support GTX, GTH and GTP Production Silicon
- Increased line rate support for GTZ Transceivers
- Support for Asymmetrical data widths on TX and RX (core generation and implementation only, not supported in simulation)
Known Issues and Limitations
- For GTH and GTP, the Wizard generates settings compatible for Production Silicon. Hardware validation of these settings is work in progress.
- The Wizard generates Verilog wrappers for GTZ. VHDL is not supported.
- For GTZ designs, the Wizard supports line rates and reference clocks shown in the GUI. No other values are tested or validated in hardware.
- It is recommended that the Beachfront module generated for GTZ designs should NOT be modified by the user. Any edits made by the user might lead to unexpected results.
- Support for Asymmetrical data widths on TX and RX (core generation and implementation only, not supported in simulation).
- Please note that Vivado flow should be used for implementation of all SSIT devices.
- Please note that the protocol templates provided by the Wizard are not characterized on hardware.
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- 7 Series FPGAs Transceivers Wizard