We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 58131

Vivado Constraints - How can I ignore timing analysis between two clock domains, including any auto-generated clocks?


In my design there are two input clocks and one of them drives an MMCM.

What is the correct command if I want to set a false path between the two clocks, including the auto-generated clocks?


In the following example constraints, the clock objects of the two input clocks are named clk1 (which drives MMCM) and clk2.
1. set_false_path -from [get_clocks -include_generated_clocks clk1] -to [get_clocks clk2]
    set_false_path -from [get_clocks clk2] -to [get_clocks -include_generated_clocks clk1]
2. set_clock_groups -asynchronous -group [get_clocks -include_generated_clocks clk1] -group [get_clocks clk2]
AR# 58131
Date 01/12/2015
Status Active
Type General Article
  • FPGA Device Families
  • Vivado Design Suite