Instantiating Multiple Cores
With multiple cores, instantiate the modules as separate components in the top-level RTL, as there are different synthesized Check Point (.dcp) files for each core.
For example, in Verilog:
core1 core_inst1 (
);core2 core_inst2 (
Instantiation templates for the cores are outputs of the Vivado Design Suite when the cores are generated and have filename extensions of .vho (for VHDL) and .veo (for Verilog).
Generating the Cores Using Out-of-Context Design Flow
For each core that will be instantiated, the component names must match the names used in the top level RTL design. For example, the component name for the first core is core1, and the component name for the second core is core2.
Choose the Generate Synthesized Checkpoint (.dcp) option to generate each core. Setting this option will launch synthesis on the IP as the output products are being generated. This is referred to as Out-of-Context (OOC) synthesis.
After the core is generated, use the Open IP Example Design option to generate the example design files and the top level XDC file.
Creating Top-Level User Constraints File
When instantiating multiple cores, each core is generated separately by the Vivado Design Suite and includes a separate top-level XDC. Merge the top-level XDC generated for each core to produce a single XDC with all the required constraints.
For each core constraint, the instance name in the XDC file must be modified to match the instance name in the top-level RTL design. For the I/O pin location constraints, change the names to match the I/O ports in the top-level design as shown in the example below:
set_property LOC AY39 [get_ports TDClk_P_1]
set_property LOC AY40 [get_ports TDClk_N_1]
set_property LOC K23 [get_ports TDClk_P_2 ]
set_property LOC J23 [get_ports TDClk_N_2]
Importing the Cores and Implementing the Design
The core only supports user clocking mode. In user clocking mode, the clocking logic is defined external to the core. An example of the external clocking module is provided as part of the provided example design.
If the reference clock (SysClk) can be shared between different Source cores, the user can use a single Source clocking module with global clock option and the clock outputs (SysClkDiv_bufg and SysClk0_bufg) of this module to drive the other Source cores.
Instantiating IDELAYCTRL Modules
The Vivado Design Suite handles the replication and placement of the IDELAYCTRL modules automatically if the IDELAYCTRLs have the same refclk and reset. In multiple core implementations, it is typical to have the same reset and refclk signals connected to the IDELAYCTRLs. In this case, only one IDELAYCTRL is needed. The software will duplicate and place the IDELAYCTRLs in the same clock regions as the associated IDELAY elements in the design.
If different refclk and reset signals are needed for IDELAYCTRL modules, then each IDELAYCTRL with associated refclk and reset needs to be instantiated in the design. For more details about IDELAYCTRL usage and design guidelines, see the appropriate Kintex-7 or Virtex-7 FPGA user guide.