AR# 58244

Design Advisory for 7 Series FPGA GTX Transceiver - RXDFEXYDEN Port Update in DFE Mode


This Design Advisory Answer Record covers the RXDFEXYDEN port for the 7 series FPGA GTX Transceiver and the correct setting for it.


The 7 Series FPGAs GTX/GTH Transceivers User Guide (UG476) shows that RXDFEXYDEN is a reserved port and should be set to 1'b1. The 7 Series FPGAs Transceivers Wizard v2.6 or earlier, in the Vivado 2013.2 and ISE 14.6 (or earlier tools) set it to 1'b0 for GTX, but the correct setting is 1'b1 (this is already set correctly to 1'b1 by the Wizard for GTH transceiver).

This is fixed for GTX in v3.0 of the Wizard in Vivado Design Suite 2013.3, and v2.7 of the Wizard in ISE Design Suite 14.7.

For any new GTX designs, the correct setting of 1'b1 should be used.

For any existing GTX designs, no update is required if using LPM mode. When using DFE mode, no update is necessary for channel insertion losses of less than 15 dB at the Nyquist frequency. For the medium and long reach applications with channel losses of 15 dB and higher in DFE mode, it is recommended to update to this value because this enhances the performance for these applications.

Answer Records for affected IPs:

XAUI and RXAUI: (Xilinx Answer 58083)

Ethernet 1000BASE-X PCS/PMA or SGMII and QSGMII: (Xilinx Answer 58460)

Ten Gigabit Ethernet PCS/PMA (10GBASE-R/10GBASE-KR): (Xilinx Answer 58461)

SRIO: (Xilinx Answer 58402)

CPRI: (Xilinx Answer 58488)

Aurora 64B66B: (Xilinx Answer 58463)

Aurora 8B10B: (Xilinx Answer 58464)

Revision History
11/22/2013 - Initial release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
42944 Design Advisory Master Answer Record for Virtex-7 FPGA N/A N/A
42946 Design Advisory Master Answer Record for Kintex-7 FPGA N/A N/A

Child Answer Records

AR# 58244
Date 08/05/2014
Status Active
Type Design Advisory