When more than 16 (but fewer than 32) BUFG components are required, pin selection and placement must be considered in order to avoid any possibility of contention of resources based on global clocking line contention, placement of clock loads, or both.
As in all other Xilinx 7 series FPGA devices, Clock-Capable I/O (CCIO) components and their associated Clock Management Tile (CMT) have restrictions on the BUFG components that they can drive in the SLR.
CCIO components in the top or bottom half of the SLR can drive BUFG components only in the top or bottom half of the SLR (respectively).
Accordingly, pin and associated CMT selection must be done in a way in which no more than 16 BUFG components are required in either the top or bottom half of all SLR components collectively.
The tools automatically assign all BUFG components in a way that allows all clocks to be driven to all SLR components without contention.