We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome,
Internet Explorer 11,
Safari. Thank you!
This Critical Warning occurs when multiple source files have the same module/entity name in them. When this module/entity is compiled the second time and subsequent times, Vivado Synthesis gives this Critical Warning.
To resolve this Critical Warning, check the following:
Make sure that a source file is only added to sources once. If the same file is added to sources multiple times (from different locations), they will need to be compiled into different libraries.
Make sure that multiple modules/entities are not using the same name.
Are any Simulation source files added to Design sources and used in Synthesis and Implementation? If this is the case, change the source file property "Used in" to "Simulation" only.
A typical cause of this critical warning is that the same Xilinx IP is instantiated more than once in the design, so there are different files with the same entity/module name in the IP sources.
The latest versions of most IPs have fixed this issue to avoid situations where different files using the same entity/module name but with different contents.
In older versions, you can use the IP in Out Of Context (OOC) mode to resolve the issue.