The following conflict occurs when the AXI QSPI IP and HWICAP IP are both used in a Vivado IPI design targeting a specific board (AC701, etc.):
In the AXI QSPI IP, if the Board Interface "spi flash" is selected, it will automatically instantiate the STARTUPE2 block. The AXI HWICAP IP requires either the STARTUPE2 block be instantiated, or an End Of Startup (EOS) input signal be connected.
The AXI QSPI IP does not provide an EOS output signal when the STARTUPE2 block is instantiated.
The tools will generate an error if there are two STARTUPE2 blocks in a design, as there is only one available per FPGA.