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AR# 58353

MIG 7 Series - Is there an alternative way to incorporate the IODELAY reset signal into a PLL lock signal without modifying HDL?


UG586 (7 Series FPGAs Memory Interface Solutions) describes, when an internal PLL drives the reference clock, the reset signal in IODELAY_CTRL needs to be incorporated into the PLL lock signal:

"If a PLL clock drives the IDELAYCTRL input clock, the PLL lock signal needs to be incorporated in the rst_tmp_idelay signal inside the IODELAY_CTRL.v module. This ensures that the clock is stable before being used."

Is there an alternative way to incorporate the reset signal into the lock signal without modifying IODELAY_CTRL.v?


The rst_tmp_idelay is driven by sys_rst. If the ref_clk PLL lock signal is incorporated into sys_rst outside MIG, it is logically the same as incorporating it into rst_tmp_idelay.

AR# 58353
Date 11/15/2013
Status Active
Type General Article
  • Artix-7
  • Kintex-7
  • Virtex-7
  • Zynq-7000
  • MIG 7 Series
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