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Vivado - ERROR: [Designutils 20-61] Pseudo-gates inferred from RTL source
When a script is run on a design containing a black box module synthesized with Synplify Pro, the following error is seen when running the link_design command:
ERROR: [Designutils 20-61] Pseudo-gates inferred from RTL source are not valid in a structural netlist [fp_top.v:32] ERROR: [Designutils 20-13] HDL Source containing RTL statements cannot be used to create a structural netlist
Below are the commands used:
read_verilog ./src/file1.v read_verilog ./src/top.v
synth_design -top top -part XC7V585TFFG1761-2 -bufg 32
link_design -top top -part XC7V585TFFG1761-2
The problem here is with the script.
The link_design command is used because of the edif file, but this is not needed when an RTL project includes an edif netlist.
Removing the link_design command removes the error.