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AR# 58412

10-Gigabit Ethernet PCS/PMA (10GBASE-R/10GBASE-KR) v3.0 (Rev. 1) and earlier - Update to RXRESETTIME transceiver CDR lock timer values

Description

In the 10-Gigabit Ethernet PCS/PMA (10GBASE-R/10GBASE-KR) v3.0 (Rev. 1) and earlier core, the RXRESETTIME value used for the transceiver CDR lock timer was calculated using the 156.25 MHz clock.

However, the value should be based on the 322.26 MHz clock which is used to clock the counter.

Solution

This issue has been fixed in the v3.0 (Rev. 2) patch updated, (see (Xilinx Answer 58656)) and in v4.0 or later of the core available in Vivado 2013.3 or later.

If using v3.0 (Rev. 1) or earlier, the RXRESETTIME can be updated in the <core_name>_local_clock_and_reset.v/vhd file.

Verilog
   
1) 

reg [19:0] rxuserrdy_counter = 20'h0;
  // Nominal wait time of 50000 UI = 757 cyles of 156.25MHz clock
  localparam [19:0] RXRESETTIME_NOM = 20'h002F5;
  // Maximum wait time of 37x10^6 UI = 560782 cycles of 156.25MHz clock
  localparam [19:0] RXRESETTIME_MAX = 20'h89000;

  // Set this according to requirements
  wire [19:0] RXRESETTIME = RXRESETTIME_NOM;


becomes:

  reg [23:0] rxuserrdy_counter = 24'h0;
  // Nominal wait time of 50000 UI = 1563 cyles of 322.26MHz clock
  localparam [23:0] RXRESETTIME_NOM = 24'h00061B;
  // Maximum wait time of 37x10^6 UI = 1156262 cycles of 322.26MHz clock
  localparam [23:0] RXRESETTIME_MAX = 24'h11A4A6;
 
  // Set this according to requirements
  wire [23:0] RXRESETTIME = RXRESETTIME_NOM;


2) near the bottom of the file:

    if(!qplllock_rxusrclk2 || gtrxreset_rxusrclk2)
       rxuserrdy_counter <= 20'h0;

 
becomes:

     if(!qplllock_rxusrclk2 || gtrxreset_rxusrclk2)
       rxuserrdy_counter <= 24'h0;


VHDL:
   
1)  

signal rxuserrdy_counter : std_logic_vector(19 downto 0) := x"00000";
  -- Nominal wait time of 50000 UI = 757 cyles of 156.25MHz clock
  signal RXRESETTIME_NOM : std_logic_vector(19 downto 0) := x"002F5";
  -- Maximum wait time of 37x10^6 UI = 560782 cycles of 156.25MHz clock
  signal RXRESETTIME_MAX : std_logic_vector(19 downto 0) := x"89000";
 
  -- Set this according to requirements
  signal RXRESETTIME : std_logic_vector(19 downto 0);


becomes:

  signal rxuserrdy_counter : std_logic_vector(23 downto 0) := x"000000";
  -- Nominal wait time of 50000 UI = 1563 cyles of 322.26MHz clock
  signal RXRESETTIME_NOM : std_logic_vector(23 downto 0) := x"00061B";
  -- Maximum wait time of 37x10^6 UI = 1156262 cycles of 322.26MHz clock
  signal RXRESETTIME_MAX : std_logic_vector(23 downto 0) := x"11A4A6";

  -- Set this according to requirements
  signal RXRESETTIME : std_logic_vector(23 downto 0);


2) near the bottom of the file:

    if(qplllock_rxusrclk2_i = '0' or gtrxreset_rxusrclk2_i = '1') then
      rxuserrdy_counter <= x"00000";


becomes:

    if(qplllock_rxusrclk2_i = '0' or gtrxreset_rxusrclk2_i = '1') then
      rxuserrdy_counter <= x"000000";


Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
58656 10-Gigabit Ethernet PCS/PMA (10GBASE-R/10GBASE-KR) v3.0 (Rev 2) - Downloadable Rev 2 patch update N/A N/A
AR# 58412
Date Created 11/15/2013
Last Updated 09/04/2014
Status Active
Type General Article
IP
  • 10 Gigabit Ethernet PCS-PMA with FEC/Auto-Negotiation for backplanes (10GBASE-KR)
  • Ten Gigabit Ethernet PCS/PMA