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AR# 58435

DDR4, DDR3, QDRIV, QDRII+, RLDRAM3, LPDDR3 UltraScale and UltraScale+ - IP Release Notes and Known Issues

Description

This answer record contains the Release Notes and Known Issues for the DDR4, DDR3, QDRII+, QDRIV, RLDRAM3, LPDDR3 UltraScale and UltraScale+ Cores and includes the following:

  • Supported Devices
  • General Information
  • Known Issues
  • Revision History

This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2014.1 and newer tool versions.

Please reference XTP025 - IP Release Notes Guide for past known issue logs and ISE support information.

MIG IP Page:

https://www.xilinx.com/content/xilinx/en/products/intellectual-property/mig.html

Solution

General Information

Supported devices can be found in the following locations:

For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado tools.

Table 1 correlates the core version to the first Vivado design tools release version in which it was included.

Table 1: Version

DDR4 VersionDDR3 VersionRLDRAM3 VersionQDRII+ VersionQDRIV VersionLPDDR3 VersionVivado Tools Version
v2.2 (Rev. 1)v1.4 (Rev. 1)v1.4 (Rev. 1)v1.4 (Rev. 1)v2.0 (Rev. 1)v1.0 (Rev. 1)2017.2
v2.2v1.4v1.4v1.4v2.0v1.02017.1
v2.1 (Rev. 1)v1.3 (Rev. 1)v1.3 (Rev. 1)v1.3 (Rev. 1)v1.2 (Rev. 1)2016.4
v2.1v1.3v1.3v1.3v1.22016.3
v2.0 (Rev. 1)v1.2 (Rev. 1)v1.2 (Rev. 1)v1.2 (Rev. 1)v1.1 (Rev. 1)2016.2
v2.0v1.2v1.2v1.2v1.12016.1
v1.1v1.1v1.1v1.1v1.02015.4
v1.0v1.0v1.0v1.02015.3
v7.1v7.1v7.1v7.12015.2
v7.0v7.0v7.0v7.02015.1
v6.1v6.1v6.1v6.12014.4
v6.0v6.0v6.0v6.02014.3
v5.0 (Rev. 1)v5.0 (Rev. 1)v5.0 (Rev. 1)v5.0 (Rev. 1)2014.2
v5.0v5.0v5.0v5.02014.1


* Starting with the release of Vivado 2015.3, the MIG wizard is no longer used. A separate wizard exists for all supported memory interface types. Therefore, the core versions reset to 1.0.

For a list of supported memory interfaces and features for UltraScale FPGAs, see the LogiCORE IP UltraScale Architecture-Based FPGAs Memory Interface Solutions Product Guide (PG150) located at:

https://www.xilinx.com/products/technology/memory-interfacing/index.htm

For a complete list of supported memory devices please refer to the attached spreadsheet called "memory_device_support_*.xlsx" where * indicates the type of memory controller.


For a list of supported frequencies for UltraScale FPGAs Memory Interfaces, see the appropriate DC and Switching Characteristics Data Sheet available in the UltraScale Documentation Center.

For supported simulators, see the Xilinx Design Tools: Release Notes Guide.

The MIG tool includes the appropriate frequency range for each specific memory interface configuration

Table 2 provides answer records for general guidance when using the MIG UltraScale core.

Table 2: General Guidance

Answer RecordTitle
(Xilinx Answer 59625)MIG UltraScale - Design Methodology Checklist
(Xilinx Answer 61304)MIG UltraScale - Clocking Guidelines and Requirements
(PG150) - DebuggingMIG UltraScale DDR4/DDR3 - Hardware Debug Guide
(Xilinx Answer 63462)MIG UltraScale - Sample CSV data file for creating Custom Parts
(Xilinx Answer 63831)MIG UltraScale - Migrating and Upgrading IP into 2015.1
(Xilinx Answer 61598)Design Advisory Master Answer Record for Kintex UltraScale FPGA
(Xilinx Answer 61930)Design Advisory Master Answer Record for Virtex UltraScale FPGA
(Xilinx Answer 62483)Design Advisory for MIG UltraScale (all memory types) - VRP pin and DCI Cascade requirements
(Xilinx Answer 68169)Design Advisory for Kintex UltraScale FPGAs and Virtex UltraScale FPGAs - New minimum production speed specification version (Speed File) required for all designs


Known and Resolved Issues

Answer RecordTitle
(Xilinx Answer 69035)
DDR4 UltraScale and UltraScale+ IP Release Notes and Known Issues
(Xilinx Answer 69036)
DDR3 UltraScale and UltraScale+ IP Release Notes and Known Issues
(Xilinx Answer 69037)
RLDRAM3 UltraScale and UltraScale+ IP Release Notes and Known Issues
(Xilinx Answer 69038)
QDRII+ UltraScale and UltraScale+ IP Release Notes and Known Issues
(Xilinx Answer 69039)
QDRIV UltraScale and UltraScale+ IP Release Notes and Known Issues
(Xilinx Answer 69040)
LPDDR3 UltraScale and UltraScale+ IP Release Notes and Known Issues


Revision History:
04/16/2014Initial release
06/04/2014Updated for 2014.2
10/01/2014Updated for 2014.3
10/16/2014Added link to Hardware Debug Guide
11/07/2014Updated for 2014.4
12/16/2014Added AR62930
01/08/2015Added AR63261
04/15/2015Updated for 2015.1 release
06/24/2015Updated for 2015.2 release
07/06/2015Added AR64887
07/09/2015Added 64923
08/07/2015Added 64946
09/30/2015 Updated for 2015.3
11/24/2015Updated for 2015.4
01/26/2015Added 66471
04/13/2016Updated for 2016.1 release
09/19/2016Added 67891
10/05/2016Updated for 2016.3 release
02/08/2017Added 61598, 61930, 62483, 64856, 68169
03/24/2017Updated for 2017.1 release, Added LPDDR3, Added 66471, 67979, 67956, 68894, 68895, 68843
04/18/2017Created Answer Records for Each Memory Controller Type
06/05/2017Updated for 2017.2

Attachments

Associated Attachments

Linked Answer Records

Child Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
62603 Virtex UltraScale FPGA VCU108 Evaluation Kit - Known Issues and Release Notes Master Answer Record N/A N/A
AR# 58435
Date 06/20/2017
Status Active
Type Release Notes
Devices
  • Virtex UltraScale
  • Kintex UltraScale
  • Virtex UltraScale+
  • Kintex UltraScale+
Tools
  • Vivado Design Suite
IP
  • MIG UltraScale