The following message occurs when generating output products for select IP cores (e.g., MIG, cdn_axi_bfm, IBERT):
MIG 7 Series:
MIG, IBERT and BFM support global synthesis only and a DCP file will not generated
for MIG, IBERT or BFM. All other IP will have DCP files generated.
Why does this message occur?
Does it only apply to the IP listed?
By default, in Vivado 2013.3 and later tools, the Out-of-Context (OOC) design Checkpoint (DCP) file will be created for IP cores when the IP core's target outputs are generated.
BFM, IBERT, 7 Series MIG and other IP do not support the DCP/OOC flow. However, the message is hard coded to list only these three IP.
In Vivado 2014.1, IPs which do not support OOC have grayed-out check boxes in Out-of-Context Setting window.
The RTL output targets need to be used for any IP core where the generation of output products results in this pop-up message.
See also: (Xilinx Answer 57037)