I have a Tcl script that was working fine in Vivado 2013.2, but when I run it in Vivado 2013.3 or later, I get and error saying that one of my IP core modules cannot be found.
For example, I have a design that instantiates of a c_addsub v12.0. This is the latest version of addsub, and the syntax and names are all correct in the instantiating module. During synthesis, the addsub IP core seems to be created as expected, but is failing in elaboration:
# open_rtl_design -part $part -name rtl_1
Starting RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:08 . Memory (MB): peak = 816.785 ; gain = 212.848
INFO: [Synth 8-638] synthesizing module 'top' [/sources/top.v:2]
ERROR: [Synth 8-439] module 'addsub' not found [/sources/top.v:17]
ERROR: [Synth 8-285] failed synthesizing module 'top' [/sources/top.v:2]
Finished RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 847.785 ; gain = 243.848
The IP is generated and has delivered its RTL. However, the module is not getting resolved and becomes a blackbox.
This error may occur in Vivado Design Suite 2013.3 for IP cores where a DCP output is not supported.
In Vivado 2013.3, the IP cores will generate the Out-of-context (OOC) Design Checkpoint by default. If the IP does not support OOC flow, the IP core could get generated (e.g., create_ip and generate_target) but not found since the flow is expecting the OOC DCP file that does not exist.
This means that some existing Tcl scripts will need to turn off the option to generate the checkpoint in order to complete.
# create cores
create_ip -vlnv xilinx.com:ip:dist_mem_gen:8.0 -module_name my_core_name
set_property generate_synth_checkpoint false [get_files my_core_name.xci]
generate_target all [get_ips my_core_name]