Version Found: v2.0 Rev1
Version Resolved: See (Xilinx Answer 54025)
In some cases, when performing a Write command followed by a Read command, the "twtr_ok" signal inside *_rld_mc.v deasserts and always remains Low. This causes the memory controller to lock up, preventing any commands from being sent to the DRAM.
This is a RTL bug found in the initialization logic of "twtr_cnt" inside the *_rld_mc.v module.
To work around the issue, the following RTL changes can be made inside *_rld_mc.v:
always @ (posedge clk)
if (rst_clk) begin
twtr_cnt <= #TCQ RLD_TWTR;twtr_cnt <= #TCQ RLD_TWTR;
prev_wr_pointer_twtr <= #TCQ 'h0;
// when 4 write requests are issued in a user clock cycle
12/18/2013 - Initial release